1. Field of the Invention
The present invention pertains to method and apparatus involving thin film ferroelectrics for use in integrated circuits. More particularly, a smooth bottom electrode structure adjacent a ferroelectric thin film layered superlattice material improves the memory retention characteristics of a ferroelectric capacitor through less imprint and longer memory retention time.
2. Statement of the Problem
Thin film ferroelectric materials are used in a variety of nonvolatile random access memory devices. For example, U.S. Pat. No. 5,600,587 issued to Koike teaches a ferroelectric nonvolatile random access memory using memory cells consisting of a ferroelectric capacitor and a switching transistor. U.S. Pat. No. 5,495,438 issued to Omura teaches a ferroelectric memory that is formed of ferroelectric capacitors connected in parallel. The capacitors have ferroelectric materials of different coercive field values and, consequently, can use or store multi-value data. U.S. Pat. No. 5,592,409 issued to Nishimura et al teaches a nonvolatile memory including a ferroelectric layer that is polarized by the impressed voltage between two gates. The polarization or memory storage state is read as a high or low current flow across the ferroelectric layer, which permits nondestructive readout. U.S. Pat. No. 5,539,279 issued to Takeuchi et al teaches a high speed one transistor-one capacitor ferroelectric memory that switches between two modes of operation including a dynamic random access memory (xe2x80x9cDRAMxe2x80x9d) mode and a ferroelectric random access memory (xe2x80x9cFERAMxe2x80x9d) mode.
FIG. 1 depicts an ideal polarization hysteresis curve 100 for ferroelectric thin films. Side 102 of curve 100 is produced by measuring the charge on a ferroelectric capacitor while changing the applied field E from a positive value to a negative value. Side 104 of curve 100 is produced by measuring the charge on the ferroelectric capacitor while changing the applied field E from a negative value to a positive value. The points xe2x88x92Ec and Ec are conventionally referred to as the coercive field that is required to bring polarization P to zero. Similarly, the remanent polarization Pr or xe2x88x92Pr is the polarization in the ferroelectric material at a zero field value. The Pr and xe2x88x92Pr values ideally have the same magnitude, but the values are most often different in practice. Thus, polarization measured as 2Pr is calculated by adding the absolute values of the actual Pr and xe2x88x92Pr values even though these values may differ in magnitude. The spontaneous polarization values Ps and xe2x88x92Ps are measured by extrapolating a linear distal end of the hysteresis loop, e.g., end 106, to intersect the polarization axis. In an ideal ferroelectric, Ps equals Pr, but these values differ in actual ferroelectrics due to linear dielectric and nonlinear ferroelectric behavior. A large, boxy, substantially rectangular central region 108 shows suitability for use as a memory by its wide separation between curves 102 and 104 with respect to both coercive field and polarization.
Presently available ferroelectric materials depart from the ideal hysteresis shown in FIG. 1. Researchers have investigated materials for use in integrated ferroelectric devices since the 1970""s, but these investigations have not yet been commercially successful due to the development of materials that depart from the ideal hysteresis. For example, U.S. Pat. No. 3,939,292 issued to Rohrer reports that early studies of ferroelectric materials for use in ferroelectric memories were performed on phase III potassium nitrate. In practice, it turned out that potassium nitrate materials had such low polarizabilities and were so badly afflicted by fatigue and imprint that the materials were practically useless in microelectronic memories. It is nearly impossible to find ferroelectrics that meet commercial requirements. The best materials for integrated ferroelectric devices are switched using a coercive field that can be obtained from conventional integrated circuit operating voltages, i.e., three to five volts (xe2x80x9cVxe2x80x9d). The materials should have a very high polarization, e.g., one exceeding twelve to fifteen microCoulombs per square centimeter (xe2x80x9cxcexcC/cm2xe2x80x9d) determined as 2Pr, to permit the construction of memories having sufficient densities. Polarization fatigue should be very low or nonexistent. Furthermore, the ferroelectric material should not imprint, i.e., the hysteresis curve should not shift to favor a positive or negative coercive field.
FIG. 2 depicts the effects of environmental stress on hysteresis curve 100. Curve 200 shows the effect of fatigue on curve 100. Fatigue reduces the separation between curves 102 and 104 defining central region 108. Central region 108 progressively becomes smaller and smaller with additional fatigue. This change in separation is due to the creation of point charge defects arising in the ferroelectric material as a consequence of polarization switching together with the associated screening effect of the charge defects on the applied field. Thus, fatigue causes the ferroelectric material to wear out over time due to repeated polarization switching.
U.S. Pat. No. 5,519,234 issued to Araujo et al teaches that the fatigue problem of curve 200 is substantially overcome by the use of layered superlattice materials, such as the xe2x80x9clayered perovskite-likexe2x80x9d materials described in Smolenskii et al xe2x80x9cFerroelectrics and Related Materials,xe2x80x9d Gordon and Breach (1984). The layered superlattice materials are capable of providing a thin film ferroelectric material wherein the polarization state may be switched up to at least 109 times with less than thirty percent fatigue. This level of fatigue endurance provides a significant advance in the art because it is at least about three orders of magnitude better than the fatigue endurance of other ferroelectrics, e.g., lead zirconium titanate (xe2x80x9cPZTxe2x80x9d) or lead lanthanum zirconium ttanate (xe2x80x9cPLZTxe2x80x9d). Prior layered superlattice material work has been done primarily with the use of a Pt/Ti bottom electrode and layered superlattice material films on the order of 1800 xc3x85 thick. The titanium is used as an adhesion layer to prevent peeling of the electrode from the substrate.
According to section 15.3 of the Smolenskii book the layered perovskite-like materials or layered superlattice materials can be classified under three general types:
(A) compounds having the formula Amxe2x88x921Bi2MmO3m+3, where A=Bi3+, Ba2+, Sr2+, Ca2+, Pb2+, K+, Na+ and other ions of comparable size, and M=Ti4+, Nb5+, Ta5+, Mo6+, W6+, Fe3+ and other ions that occupy oxygen octahedra;
(B) compounds having the formula Am+1, MmO3m+1, including compounds such as strontium titanates Sr2TiO4, Sr3Ti2O7 and Sr4Ti3O10; and
(C) compounds having the formula AmMmO3m+2, including compounds such as Sr2Nb2O7, La2Ti2O7, Sr5TiNb4O17, and Sr6Ti2Nb4O20.
Smolenskii pointed out that the perovskite-like layers may have different thicknesses, depending on the value of m, and that the perovskite AMO3 is in principal the limiting example of any type of layered perovskite-like structure with m=infinity. Smolenskii also noted that if the layer with minimum thickness (m=1) is denoted by P and the bismuth-oxygen layer is denoted by B, then the type I compounds may be described as . . . BPmBPm . . . Further Smolenskii noted that if m is a fractional number then the lattice contains perovskite-like layers of various thicknesses, and that all the known type I compounds are ferroelectrics.
Despite the tremendous improvements in low fatigue ferroelectrics attributable to layered superlattice materials, there remains an imprint problem that is typified by curve 202 of FIG. 2. Curve 202 shows that environmental stresses can imprint curve 100 by shifting it to the right or left. This imprinting occurs when the ferroelectric material is subjected to repetitive unidirectional voltage pulses. Some imprinting also occurs as a result of normal hysteresis switching. The ferroelectric material retains a residual polarization or bias that shifts sides 102 and 104 in a positive or negative direction with respect to the applied field. Thus, curve 202 has been shifted in a positive direction 204 by repeated negative pulsing of a ferroelectric capacitor. A shift in the opposite direction could also occur due repetitive pulsing by opposite voltage. This type of pulsing represents what happens to the ferroelectric materials as a consequence of repeated unidirectional voltage cycling, such as the sense operations in FERAMs. Imprint can be so severe that the ferroelectric material can no longer retain a polarization state corresponding to a logical 1 or 0 value.
U.S. Pat. No. 5,592,410 issued to Verhaeghe refers to the ferroelectric imprint phenomenon as xe2x80x98compensation.xe2x80x99 The ""410 patent teaches that the imprint problem can be reversed by pulsing voltage during the write cycle to return the hysteresis loop towards the unimprinted position of curve 100, as compared to curve 202. Thus, the imprint problem is reversed by special write operations in which the pulsed voltage is opposite the switching voltage. Still, the recommended voltage pulsing does not address the entire problem because the imprint phenomenon is a partially irreversible one. The observed imprinting reflects corresponding changes in microstructure of the ferroelectric crystal, e.g., the creation of point charge defects with associated trapping of polarized crystal domains. These changes in microstructure are not all reversible.
FIG. 3 depicts the deleterious effects of fatigue and imprinting on ferroelectric memory read/write control operations. Memory control logic circuits require a minimum polarization separation window, which is represented by shaded region 300. Region 300 must be large enough to produce a sufficient read-out charge for memory operations, e.g., for the operation of memory sense amplifier circuits. An initial 2Pr separation window 302 declines over the lifetime of the ferroelectric memory device along tracks 304 and 306 until, after about ten years or so of constant normal use, the separation between tracks 304 and 306 is too small for conducting memory operations. This lifetime of normal use follows stress time line 308. Curve 310 is a polarization hysteresis curve from the same material that produced curve 100, but is measured on decline at a point in time along tracks 304 and 306. The remanent polarization values Rms and Rmn correspond to +Pr and xe2x88x92Pr for the fatigued and imprinted material. Rms and Rmn are defined as remanent polarization at zero field in the fatigued hysteresis curve 310. Arrow 312 shows a quantity of positive polarization retention loss, which is primarily due to fatigue. Arrow 314 shows a quantity of negative polarization imprint loss, which is primarily caused by imprint shifting of curve 312 relative to curve 100. Arrow 316 shows a quantity of voltage center shifting of curve 312 relative to curve 100. This voltage center shifting indicates imprinting of the ferroelectric material.
There remains a need for ferroelectric thin film capacitors that resist fatigue well, have long memory retention times, and are substantially free of the imprint problem.
It has been discovered that the imprint phenomenon represented as curve 202 in FIG. 2 is affected by surface irregularities on the ferroelectric film, e.g., those corresponding to hillocks on the bottom electrode in a thin film ferroelectric capacitor device or similar surface irregularities on the top of the ferroelectric film. In particular, the prior art Pt/Ti bottom electrodes form sharp hillocks that are especially prone to increase the amount of imprinting. Thus, ferroelectric capacitors having electrodes with sharp irregularities offer inferior electronic performance in integrated memories.
The present invention overcomes the problems outlined above by providing an essentially smooth or hillock-free bottom electrode for use in combination with layered superlattice materials. The ferroelectric materials are specially processed in deposition to present a similarly smooth surface for receipt of a top electrode. The layered superlattice materials resist fatigue well and their conformity to the smooth bottom electrode improves their imprint performance in integrated ferroelectric memories, such as FERAMs.
The smooth electrodes also permit the use of increasingly thinner films of layered superlattice materials without shorting of the ferroelectric capacitors. The thin films show a surprising improvement in their memory retention windows because memory retention windows in the thinner materials can have a greater magnitude than exists in comparable thicker materials. One would expect just the opposite effect because a greater number of oriented ferroelectric domains in the thicker materials should provide a greater cumulative polarization effect, but this greater cumulative polarization effect is not observed in practice. Thus, the use of smooth electrodes and thin films permits the construction of much better ferroelectric memories.
A thin film ferroelectric capacitor according to the present invention includes a bottom electrode having a first smooth surface, a ferroelectric thin film layered superlattice material, and a top electrode having a second smooth surface. The most preferred layered superlattice materials are strontium bismuth tantalate and strontium bismuth niobium tantalate. The ferroelectric thin film layered superlattice material contacts the smooth surfaces of the electrodes and has a thickness ranging from 500 xc3x85 to 2300 xc3x85. A smooth surface on one of the electrodes is hereby defined as one in which all surface irregularity features protruding towards the thin film ferroelectric layered superlattice material protrude a distance less than twenty percent of the thickness in the ferroelectric thin film layered superlattice material thickness. It is also preferred that substantially all of the surface irregularities on the smooth electrode are rounded and essentially free of acute angles. Another way of defining a smooth surface is that the surface is smoother, i.e., having surface irregularities that are less sharp, less tall, and less numerous, than the surface irregularities of a comparable 2000 xc3x85/200 xc3x85 thick Pt/Ti stacked electrode deposited on silicon which has been annealed while exposed to oxygen at 500xc2x0 C. to 800xc2x0 C. for one hour.
Ferroelectric thin film layered superlattice materials for use in the invention typically have thicknesses ranging from 500 xc3x85 to 2300 xc3x85. Thicknesses above this range are also useful, though they are seldom needed. A more preferred range of layered superlattice material thickness is from 500 xc3x85 to 1100 xc3x85. This range is even more preferably from 500 xc3x85 to 1000 xc3x85, and is most preferably from 500 xc3x85 to 800 xc3x85. The prior art does not show layered superlattice materials having these small thicknesses which are less than about 1300 xc3x85.
Ferroelectric capacitors of the invention demonstrate superior electronic performance. For example, the ferroelectric thin film layered superlattice material is capable of providing a 3 V polarization or charge separation window of at least 7 xcexcC/cm2 after being fatigued by 1010 cycles of 6 V square wave switching at 125xc2x0 C. These 6V switching pulses are very high, as compared to normal integrated circuit operating voltages and, consequently, tend to accelerate fatigue. The 7 xcexcC/cm2 separation window is sufficient for proper interaction with conventional integrated memory control logic circuits. The separation window increases as film thickness decreases down to about 500 xc3x85. Layered superlattice material films thinner than about 500 xc3x85 crystallize differently and show porosity along grain or domain boundaries, which makes them unsuitable for use in ferroelectric capacitors.
Another aspect of superior electronic performance in the ferroelectric thin film layered superlattice materials according to the invention is superior resistance to imprinting. The ferroelectric thin film layered superlattice materials are also capable of demonstrating a hysteresis shift of less than 0.11 V corresponding to the 3 V polarization separation window after 1010 cycles of 6 V square wave switching, as described above.
Yet another aspect of superior electronic performance is the development of ultra thin ferroelectric layered superlattice material films that are essentially fatigue free. The use of smooth electrodes permits the use of ferroelectric thin films having less than about 2% of 2Pr degradation after being switched 1010 cycles using a 1.5 V triangular wave at 10,000 Hz. This exceptional ferroelectric performance comes from ultra thin films, e.g., those ranging from 500 xc3x85 to 800 xc3x85 in thickness.
In a preferred embodiment, the bottom electrode includes a platinum layer deposited on a titanium dioxide layer.
In another preferred embodiment, the bottom electrode includes a platinum layer deposited on a metal nitride, e.g., TiN, diffusion barrier layer on a titanium adhesion layer.
In less preferred embodiments, the bottom electrode includes a platinum layer on a titanium adhesion layer. These embodiments are less preferred because additional processing is required to provide a bottom electrode that is essentially free of sharp hillocks. Copending application Ser. No. 08/427,897 filed Apr. 26, 1995, and Ser. No. 08/473,432 filed Jun. 7, 1995, show methods of making Pt/Ti stacked electrodes having essentially smooth surfaces, and are hereby incorporated by reference to the same extent as though fully disclosed herein. The ""897 and ""432 applications are commonly owned with the present application. The ""897 application teaches an electrode having an intermetallic barrier region formed of titanium adhesion metal and platinum. The metals are annealed at 600xc2x0 C. to 800xc2x0 C. for 30 minutes to 2 hours under a temporary capping layer of metal oxide, which is subsequently removed by an HF enchant and replaced by a second platinum layer. The ""432 application teaches the use of a layered superlattice material thermal stress buffer layer interposed between the Pt/Ti stacked bottom electrode and the underlying substrate, e.g., a silicon wafer. The top electrode is preferably platinum.
The process of making the ferroelectric capacitors includes careful control of thermal process conditions. A smooth bottom electrode is formed wherein substantially all surface irregularity features on a bottom electrode are rounded and essentially free of acute angles. This smoothness derives from a proper selection of materials and anneal temperatures. For example, the need for smoothness requires a platinum on titanium dioxide electrode to be annealed under oxygen at a temperature of not more than almost exactly 450xc2x0 C.
A liquid precursor is deposited on the bottom electrode to provide a precursor film. The precursor film is capable of yielding a ferroelectric layered superlattice material upon drying and annealing of the precursor film. Drying of the precursor film is done at a temperature less than 400xc2x0 C. to provide a dried precursor residue. The dried precursor residue is soft baked using rapid thermal processing (xe2x80x9cRTPxe2x80x9d) at an RTP temperature ranging from 525xc2x0 C. to 725xc2x0 C. for a period of time ranging from thirty seconds to five minutes. The RTP temperature more preferably ranges from 625xc2x0 C. to 650xc2x0 C., and is most preferably 650xc2x0 C., which is the highest temperature that consistently produces a smooth upper surface on the resultant soft baked precursor residue. The soft baked precursor residue is annealed in a diffusion furnace under oxygen at an anneal temperature ranging from 500xc2x0 C. to 650xc2x0 C. The anneal temperature more preferably ranges from 520xc2x0 C. to 560xc2x0 C., and is most preferably 550xc2x0 C., which is just barely sufficient to crystallize the ferroelectric layered superlattice material from the soft baked precursor residue.
Other features, objects, and advantages will become apparent to those skilled in the art upon reading the detailed description below in combination with the accompanying drawings.